`include "defines.v"
module mioc(
	input wire mem_ce,
	input wire[31:0] addr,
	input wire[31:0] wdata,
	input wire write_ce,
	input wire[3:0] sel, //字节选择信号
	output wire[31:0] rdata,
	
	//与ram连接
	input wire[31:0] ramRdData,
	output reg ramCe,
	output wire ramWe,
	output wire[31:0] ramWData,
	output wire[31:0] ramAddr,
	output wire[3:0] ramSel,
	
	//与IO连接
	input wire[31:0] ioRdData,
	output reg ioCe,
	output wire ioWe,
	output wire[31:0] ioWData,
	output wire[31:0] ioAddr,
	output wire[3:0] ioSel
);
	always@(*)
		if(mem_ce == `RamEnable)
			if(addr[31:2] < `DataMemCapacity)
			begin
				ramCe = `RamEnable;
				ioCe = `RamDisable;
			end
			else
			begin
				ramCe = `RamDisable;
				ioCe = `RamEnable;			
			end
		else
		begin
			ramCe = `RamDisable;
			ioCe = `RamDisable;
		end
		
		
		
	assign ramWData = wdata;
	assign ramAddr = addr;
	assign ramWe = write_ce;
	assign ramSel = sel;
	
	assign ioWData = wdata;
	assign ioAddr = addr - 256;
	assign ioWe = write_ce;
	assign ioSel = sel;
	
	assign rdata = (ramCe == `RamEnable)? ramRdData : ioRdData;
endmodule

